Semiconductor manufacturers have the cost saving goal of detecting and screening out defective integrated circuits (ICs) as early as possible in the manufacturing process. In addition, the requirement of supplying "known good die" to multi-chip module (MCM) manufacturers has increased the importance of this goal. In addition, many manufactured ICs will operationally fail within a first few months or weeks of use due to processing defects. This early failure is known as infant mortality. Typically, customers do not desire to receive a product that will simply fail in a short period of time and therefore high temperature testing can be performed on ICs for extended periods of time and before shipping to ferret out infant mortality product before shipping product to a customer.
During a typical semiconductor manufacturing process, a plurality of integrated circuits are formed as individual die on a semiconductor wafer. At present, each semiconductor wafer generally has dozens to hundreds of individual die formed thereon in some two-dimensional pattern (usually a row/column approach). As integration geometries decrease and the size of semiconductor wafers increase, the number of integrated circuit die formed on each wafer will increase.
Once the die are formed on the semiconductor wafer, the die are then tested to determine which die are functional and which die are not functional. In most testing procedures, each die is probed using very costly probe equipment while the die are still in wafer form. The presently available probe equipment is capable of only testing one or a few die at a time, and does not catch infant mortality but only functionally failing parts (infant mortality parts are sure to fail at a soon-to-come later time). The presently available probe equipment contacts each bonding pad on an individual die with a separate probe needle.
Typically probe testing requires that each die is probed in order to determine whether each die passes a very basic opens/shorts test (e.g. a test for electrical opens or electrical shorts). In most cases, a full functional test is also performed using the probe equipment to ensure that an adder adds, that a memory stores, etc. However, no reliability testing (testing projected failure of a part over time which includes infant mortality) is performed because it would be too costly to tie up the probe equipment testing one or a few die at a time for the many hours required for reliability testing.
The purpose of the wafer level probe test is to determine, as early as possible in the manufacturing process, whether each individual die is defective or not. The earlier a defective die is detected, the less money is wasted on further processing of defective die. Bad die are marked via ink or are retained via a computer program to ensure that these bad die are discarded.
The die are then separated or singulated (via a scribe line dicing process) into individual die using any one of a variety of singulation techniques. In most cases, each good die is then packaged in an integrated circuit package. Once the die have been packaged, thorough electrical testing is performed on each of the packaged integrated circuits. The purpose of the thorough electrical testing is to determine whether each packaged integrated circuit properly performs the functionality specified by the semiconductor manufacturer. The tested, packaged integrated circuits are then sold.
In some cases, the packaged integrated circuits also undergo a reliability testing procedure called burn-in. Burn-in testing involves the testing of an integrated circuit for an extended period of time while the temperature of the integrated circuit is elevated above room temperature. This test method finds infant mortality failures. In some cases, the heat generated by the integrated circuit itself is sufficient to elevate the temperature of the integrated circuit. In other cases, the temperature of the integrated circuit is raised by an apparatus external to the integrated circuit (e.g. a burn-in oven in which the packaged integrated circuits are placed).
Alternately, instead of or in addition to burn-in testing, cold temperature reliability testing may be performed. Cold temperature reliability testing involves the testing of an integrated circuit for an extended period of time while the temperature of the integrated circuit is decreased below room temperature. Therefore, reliability testing is performed to not only ensure functionality of the die, but ensure that the die can survive reasonable changes in environment and operation over extended periods of time.
Typically, the die can be burn-in tested on a die-by-die basis after packaging, or can be burned-in on a wafer-level basis (i.e., all die on the wafer are burned-in in parallel). To burn in all ICs in parallel on a wafer, a top level of conductive material is placed on the wafer with contact areas for the top layer being formed over areas not occupied by IC die (therefore, the area of the wafer is increased or special processing is needed to place the top level of conductive material in a place where no other structures lie on the wafer). The top level of conductive material is routed to all the tens or hundreds of ICs on the wafer, which in many cases can create high current requirements since modern ICs can dissipate 1-50 Watts of power easily. The high power requires that the top layer of metal be thick and/or wide to provide for the potentially large current draw. Therefore, the top layer of metal for current wafer burn-in is constrained by current limitations and requires special processing (the equipment for this special processing being costly to buy and maintain, costly in space since it takes up room in an IC facility, cumbersome since it decreases throughput, etc.). Therefore, a need exists for a burn-in methodology that reduces high current problems and does not require special processing (i.e., integrated better with existing equipment and process flows).